Method of fabricating a COF utilizing a tapered IC chip and chip mounting hole

ABSTRACT

A method of manufacturing a COF package comprises the steps of providing a resin film substrate with a hole for receiving a chip, providing an IC chip having electrodes, inserting the IC chip into the hole so as to fix it with its electrodes exposed above the substrate surface, and forming a circuit pattern on the substrate surface for connection with the electrodes. The hole and the IC chip are tapered, and the IC chip is secured in the hole with sealant or adhesive.

FIELD OF ART

The present invention relates to a method of manufacturing a COF packagesuch as a non-contact type ID card.

BACKGROUND ART

Heretofore, COF (Chip on Film) packages such as a non-contact type IDcard and a non-contact type tag have been manufactured by variousmethods.

As an example there is known a method in which bumps (salientelectrodes) formed on an IC chip are aligned with electrodes of anantenna circuit formed on a resin film substrate, then the IC chip ispressed to effect flip chip bonding, and subsequently resin is filledinto a slight gap (or a slight space) between the resin film substrateand the IC chip, that is, under-fill is performed.

As another example there is known a method in which a semi-hardenedanisotropic conductive film is affixed to electrodes of an antennacircuit formed on a resin film substrate, then bumps (salientelectrodes) formed on an IC chip are aligned with the electrodes of theantenna circuit, then the IC chip is pressed under heating to bond theelectrodes and harden the anisotropic conductive film.

Thus, in each of these known methods, an IC chip is mounted in a stackedform onto the surface of a substrate having an antenna circuit, and thusa limit is encountered in reducing the package thickness.

In an effort to avoid such an inconvenience, for example as is disclosedin Japanese Published Examined Patent Application No. 70272/1991, therehas been proposed a method (hereinafter referred to as the IC chipburied type manufacturing method) in which a resin film substrate havinga chip mounting hole and an IC chip having electrodes are provided, thenthe IC chip is inserted and fixed into the chip mounting hole so as toexpose the electrodes above the substrate surface, and thereafter acircuit pattern for connection with the electrodes is formed on thesubstrate surface.

In this known IC chip buried type manufacturing method, however, sincethe IC chip is inserted into the chip mounting hole formed in the resinfilm substrate, it is necessary that the chip mounting hole be formedlarger than the IC chip, with consequent formation of a slight gap (or aslight space) between the inserted IC chip and the mounting hole.Therefore, a resin of the same quality as the substrate is filled intothe slight gap, followed by hot pressing for fusion-bonding of the two.

In the fusion-bonding, the resin film substrate itself, which is thin,is apt to be deformed and there further arises a problem that the ICchip shifts under a pressing force and its position varies and does notbecome fixed. Due to this problem, at the time of forming a circuitpattern onto the substrate surface after the insertion and fixing of theIC chip into the chip mounting hole, it is troublesome to form thecircuit pattern accurately with respect to the electrodes on the ICchip, that is, in such a state as is free from a larger positionaldeviation than a predetermined limit, and thus the constant qualitycannot be maintained sufficiently.

As one means for solving this problem there has been proposed theadoption of a resin pouring method instead of the aforesaid hotpressing, but the aforesaid means involves complicated manufacturingsteps and requires a long processing time. For these reasons it is notsuitable for mass production of COF packages and the adoption thereofhas so far been difficult.

The present invention has been accomplished in view of such drawbacksand it is a first object of the invention to provide a method ofmanufacturing a COF package which, when a COF package is to be obtainedby the IC chip buried type manufacturing method, permits an IC chip tobe buried in such a state as is free from a larger positional deviationthan a predetermined limit and which thereby affords a COF package of aconstant quality. It is a second object of the present invention topermit mass production of COF packages having a constant quality.

DISCLOSURE OF THE INVENTION

According to the present invention, for achieving the above firstobject, there is provided a method of manufacturing a COF package,comprising the steps of providing a resin film substrate having a chipmounting hole, providing an IC chip having electrodes, inserting the ICchip into the hole so as to fix it with its electrodes exposed above asurface of the substrate, and forming a circuit pattern on the substratesurface for connection with the electrodes, wherein the chip mountinghole and the IC chip are tapered, and the IC chip is fixed into the chipmounting hole with a sealant or an adhesive.

According to the present invention, for achieving the above secondobject, the resin film substrate is subjected to pressing with use of aheated tapered die to form the chip mounting hole, or a wafer havingconductor patterns is cut with use of a grinding rotary cutter so as toprovide tapered cut faces, thereby providing the IC chip havingelectrodes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a mode in which a tapered IC chip isinserted into a tapered chip mounting hole formed in a resin filmsubstrate;

FIG. 2 is a diagram showing a tapered IC chip obtained by cutting awafer shown in FIG. 5;

FIG. 3 is a diagram showing a tapered IC chip obtained by cutting awafer shown in FIG. 6;

FIG. 4 is a diagram showing a mode in which a wafer is cut into a chipsize;

FIG. 5 is a diagram showing an example of a wafer for fabricating atapered IC chip;

FIG. 6 is a diagram showing another example of a wafer for fabricating atapered IC chip;

FIG. 7 is a diagram showing a mode in which a passivation film isformed;

FIG. 8 is a partially enlarged diagram of FIG. 5;

FIG. 9 is a partially enlarged diagram of FIG. 6;

FIG. 10 is a diagram showing a mode in which projections are formed in atapered chip mounting hole;

FIG. 11 is a diagram showing a COF package;

FIG. 12 illustrates a series of steps for replenishing a sealant or anadhesive, in which (a) is a diagram showing a state before replenishmentand (b) is a diagram showing a state after replenishment by stencilprinting; and

FIG. 13 illustrates another series of steps for replenishing a sealantor an adhesive, in which (a) is a diagram showing a state beforereplenishment, (b) is a diagram showing a state in which a sealant or anadhesive has been applied onto a resin film substrate, and (c) is adiagram showing a state in which the sealant or adhesive applied ontothe resin film substrate has been partially removed, allowing electrodesof a tapered IC chip to be exposed.

FIG. 14 is a partial top plan view of a circuit pattern on a substratesurface.

BEST MODE FOR CARRYING OUT THE INVENTION

In the present invention, as shown in FIG. 1, a tapered IC chip 4 havingelectrodes 3 is inserted into a tapered chip mounting hole 2 formed in aresin film substrate 1 and is fixed with a sealant or adhesive 5 tofabricate a COF package.

The resin film substrate 1 is not specially limited insofar as it isformed of an insulating resin. But a resin substrate suitable forforming the tapered chip mounting hole 2 therein is selected, e.g., apolyester alloy film substrate. Also as to a machining method forforming the hole, a predetermined machining method is selected inrelation to the resin film substrate 1 selected. For example, in thecase of a polyester alloy film substrate, there is selected a methodwherein the substrate is pressed with a heated tapered die. According tothis method, the tapered chip mounting hole 2 can be machined rapidlywith a certain accuracy.

More specifically, a nickel die having plural projections similar inshape to the tapered IC chip 4 is heated to 240° C. and is pushedagainst a polyester alloy film substrate, then after pressing for 10seconds, the die is cooled quickly to 80° C., followed by removal of thedie, whereby it is possible to machine a tapered chip mounting hole 2having a hole pitch of 10 mm long by 10 mm wide, an opening portion of1.2 mm×1.6 mm, and a depth of 50 μm.

The tapered chip mounting hole 2 is formed as a non-through hole, butthe “non-through hole” as referred to herein may be a non-through holeformed by first forming a through hole in the resin film substrate 1 andby subsequently closing one-end opening of the through hole by apredetermined method. The tapered chip mounting hole 2 is formed in apredetermined shape conforming to the shape of the tapered IC chip 4,but is generally in a square or rectangular shape in plan.

As to the depth D of the tapered chip mounting hole 2, a predetermineddepth is selected correspondingly to the thickness of the tapered ICchip 4 having the electrodes 3, i.e., there is selected such a depth aspermits the tapered IC chip 4 to be inserted into the chip mounting hole2 with only the electrodes 3 exposed above the substrate surface.Further, an angle of 45 degrees is generally selected as a taper angleθa of the tapered chip mounting hole 2, provided a desired angle can beselected in the range of 45° to 60° as necessary. Also as to a machiningpattern, a predetermined pattern is selected as necessary.

On the other hand, a taper angle θb (see FIGS. 2 and 3) of the taperedIC chip 4 having the electrodes 3 is set equal to that (θa) of thetapered chip mounting hole 2, but the tapered IC chip 4 may bemanufactured by any method.

For example, the tapered IC chip 4 may be fabricated in such a manner asshown in FIG. 4, in which a wafer 7 having conductor patterns 6 forforming the electrodes of IC chips is cut into a chip size so as toprovide tapered cut faces. As an example of means for the cutting thereis mentioned a grinding rotary cutter 16 having a disc shape. There maybe adopted any other type of cutting means, but the cutting method justmentioned above is suitable for mass production of the tapered IC chip 4having the electrodes 3.

The tapered IC chip 4 is formed in a square or rectangular shape in planand all of its four side faces are tapered at the taper angle θb. Asshown in FIGS. 5 and 6, it is preferable that the wafer 7 havingconductor patterns 6 be formed with insulating patterns 8 for insulatingthe conductor patterns 6 through a passivation film. The formation ofthe insulating patterns 8 at this stage is not always necessary, but inthis case it is necessary to form the insulating patterns 8 after the ICchips 4 obtained by cutting the wafer 7 have been fixed to thesubstrate. As shown in FIG. 7, the aforesaid passivation filmcorresponds to a passivation film 15 which covers the wafer surface(i.e., chip surface).

As shown in FIG. 8 which is a partially enlarged view of FIG. 5, theconductor patterns 6 may each have a two-layer structure in which anunder-barrier metal layer 10 is formed on an underlying first conductorlayer 9 (conductor pattern electrode), or may each have a three-layerstructure in which the under-barrier metal layer 10 is formed on theunderlying first conductor layer 9 (conductor pattern electrode) and asecond conductor layer 11 is formed on the under-barrier metal layer 10,as shown in FIG. 9 which is a partially enlarged view of FIG. 6.

In those structures, the deterioration of the first conductor layer 9can be prevented by the under-barrier metal layer 10, and theunder-barrier metal layer 10 also plays the role of securing theconnection between the electrodes of the IC chip and externalelectrodes. Accordingly, tapered IC chips 4 a and 4 b (see FIGS. 2 and3) having electrodes 3 can be obtained by cutting the wafers 7 shown inFIGS. 5 and 6 into a chip size.

It is preferable that the sealant or adhesive 5 be applied in apredetermined amount to the tapered chip mounting hole 2 beforeinserting the tapered IC chip 4 a or 4 b having electrodes 3 into thetapered chip mounting hole 2. Where required, the sealant or adhesive 5may be applied to, for example, a lower end face (a lower surface on theside where the chip is inserted into the tapered chip mounting hole 2)of the tapered IC chip 4 having electrodes 3.

To improve rolling of the sealant or adhesive 5, it is preferable thatbottom projections 12 or side projections 13 be formed in the taperedchip mounting hole 2, as shown in FIG. 10. Alternatively, it ispreferable to form a bleeding hole 20 in the bottom wall of the hole, asshown in FIG. 11. With the bleeding hole 20, it is possible to effectthe relief of air at the time of heat-hardening of the sealant oradhesive 5 after insertion of the tapered IC chip 4 into the taperedchip mounting hole 2.

As to the sealant or adhesive 5, a predetermined one can be selected,e.g., an epoxy, acrylic or polyimide-based sealant or adhesive.Generally, it suffices to apply the sealant or adhesive 5 to only thebottom wall of the hole (see FIG. 1). However, the sealant or adhesive 5may be applied to only the side wall of the hole or both side wall andbottom wall of the hole as necessary. Also as to the application method,there may be used any method, e.g., a method using a transfer pin.

As to the method for inserting the tapered IC chip 4 into the taperedchip mounting hole 2, it is optional whether the method involvesinserting all tapered IC chips 4 into plural tapered chip mounting holes2 respectively at a time or inserting tapered IC chips 4 one by one intothe tapered chip mounting holes 2. Generally, the latter is selectedbecause the former involves difficulty. For example, there may beadopted a method wherein tapered IC chips 4 are each chucked by asuction nozzle and transferred, then are inserted one after another intotapered chip mounting holes 2 located at predetermined positions.

Through the above-mentioned steps each tapered IC chip 4 havingelectrodes 3 is inserted into each tapered chip mounting hole 2 formedin the resin film substrate 1 and both are fixed together by the sealantor adhesive 5. Subsequently, as shown in FIG. 11, a circuit pattern 14for connection with the electrodes 3 on the tapered IC chip 4 is formedon the resin film substrate 1 by a suitable method such as screenprinting and the whole of the substrate surface with the circuit pattern14 formed thereon is sealed with a resin film or the like.

Thus, in the present invention, the chip mounting hole and IC chip areformed in a tapered shape and the IC chip is fixed to the chip mountinghole with a sealant or adhesive. Therefore, the IC chip can be buried insuch a state as is free from a larger positional deviation than apredetermined limit. Consequently, at the time of forming a circuitpattern onto the substrate surface, the circuit pattern can be formedaccurately with respect to electrodes of the IC chip, that is, it can beformed so as not to be dislocated to a larger extent than apredetermined limit, thus affording a COF package of a constant quality.

If the sealant or adhesive 5 is applied too much to the tapered chipmounting hole 2, a surplus portion of the sealant or adhesive will bepushed out onto the surface of the resin film substrate when the taperedIC chip 4 is inserted into the hole 2, thus obstructing the formation ofthe circuit pattern 14 (see FIG. 11). To avoid this inconvenience, it ispreferable that the sealant or adhesive 5 be applied to the tapered chipmounting hole 2 locally in a small amount required for fixing thetapered IC chip 4 temporarily, without applying the sealant or adhesive5 to the whole surface of the tapered chip mounting hole 2.

In this case, however, there is formed a slight gap between the taperedIC chip 4 inserted and temporarily fixed into the tapered chip mountinghole 2 and the same hole, so it is preferable to replenish the sealantor adhesive 5 into the said gap in a vacuum atmosphere.

For example, in FIG. 12(a), the tapered chip mounting hole 2 and thetapered IC chip 4 are contacted with each other at the respectivetapered faces and the chip 4 is fixed temporarily at bottom cornerportions of the hole 2 by means of sealant or adhesive portions 5 a and5 b which are applied separately from each other to bottom cornerportions of the hole 2. In this case, as shown in FIG. 12(b), thesealant or adhesive 5 may be replenished by stencil printing in a vacuumatmosphere while utilizing a filling hole 21 formed in the bottom wallof the hole.

In the same figure, with movement of a squeegee 23, the sealant oradhesive 5 fed onto a stencil plate 22 is pushed into the filling hole21 through an aperture 24 formed in the stencil plate 22 and is filledinto the foregoing gap. The filling hole 21 and the bleeding hole 20 mayserve in common to each other.

In FIG. 13 there is shown another example. In this example, which isdifferent from the above example shown in FIG. 12, the tapered chipmounting hole 2 and the tapered IC chip 4 are not contacted at therespective tapered faces, but the sealant or adhesive 5 is interposedbetween the two.

In this case, the sealant or adhesive 5 is applied in a vacuumatmosphere onto the surface of the resin film substrate 1 above whichthe electrodes 3 of the tapered IC chip 4 are exposed, and is therebyfilled into the slight gap between the tapered chip mounting hole 2 andthe tapered IC chip 4.

Thereafter, in order that the electrodes 3 of the tapered IC chip 4 thuscoated with the sealant or adhesive 5 may be exposed, the sealant oradhesive 5 on those electrode portions is removed. In the latterexample, it is preferable to use a photosensitive insulating material asthe sealant or adhesive 5. But, in case of using such a photosensitiveinsulating material, the material is removed by development so as toexpose the electrodes 3 of the tapered IC chip 4.

In both examples described above, the vacuum atmosphere is held in therange of 13.3 Pa to 665 Pa. Thus, in the present invention, how to applythe sealant or adhesive is not specially limited insofar as the chipmounting hole and the IC chip are tapered.

The processing flow in the IC chip buried type manufacturing methodaccording to the present invention has been outlined above. Themanufacturing method will be described below in more detail by way ofworking Examples.

EXAMPLE 1

A back side of a wafer with aluminum electrodes (a first conductor layer9 of conductor pattern 6) formed on a surface thereof was polished toobtain a 50 μm thick wafer 7. The area for each IC chip on the wafersurface was 1.6 mm×2.0 mm and a pair of aluminum electrodes of a squareshape with one side being 100 μm were formed at diagonal positions in anouter periphery portion of the chip area.

The wafer 7 was treated with a weakly acidic solution to remove an oxidefilm formed on the surface of each aluminum electrode and, afteractivation treatment, the wafer was immersed in an electroless nickelplating bath at 90° C. for 20 minutes to form a nickel plating layer ofabout 3 μm on only each of the aluminum electrodes, then the wafer wasimmersed in an electroless gold plating bath at 90° C. for 10 minutes toform a gold plating layer of about 0.1 μm on the nickel plating layer.

The nickel/gold plating layer corresponds to the under-barrier metallayer 10 (generally called UBM) which is for preventing deterioration ofthe aluminum electrodes and for securing the connection between the ICchip electrodes and external terminals.

Next, using a screen printing machine, a solder resist was printed ontothe upper surface of the wafer except the portions where the aluminumelectrodes were formed, followed by ultraviolet radiation using a UVlamp, allowing the solder resist to harden to form an insulating pattern8 having a thickness of 20 μm.

Then, using the screen printing machine, a conductive paste with silvergrains dispersed therein was filled by printing into the aluminumelectrode-formed portions (insulating pattern 8—free portions) as openportions and was hardened under heating to form a second conductor layer11 of each conductor pattern 6 (see FIGS. 6 and 9).

Next, the surface (the side where the conductor patterns 6 are formed)of the wafer 7 was affixed to a support film and thereafter the waferwas subjected to full cutting (only the wafer was cut) into a chip sizeof 1.6 mm×2.0 mm from its back side with use of a diamond blade having abevel-cut tip to obtain tapered IC chips 4 b with electrodes 3 formedthereon and having a taper angle θb of 45° (see FIG. 3).

The tapered IC chips 4 b thus obtained from the wafer were then removedfrom the support film and arranged in regular order on a palletfabricated by a nickel electroforming method.

On the other hand, using a nickel die having projecting portionscorresponding to the chip shape and each formed in a predeterminedpattern, plural tapered chip mounting holes 2 were formed in a resinfilm substrate 1 constituted by a 100 μm thick polyester alloy film.More specifically, the nickel die was heated to 240° C. and was pressedunder pressure for 10 seconds while pushed against the resin filmsubstrate 1, then was cooled rapidly to 80° C., whereupon it wasseparated from the substrate.

Tapered chip mounting holes 2 thus formed each had an opening size of1.6 mm×2.0 mm, a depth D of 70 μm, and a taper angle θa of 45°. The holepitch was 10 mm longitudinally and 50 mm transversely.

Thereafter, the sealant or adhesive 5, which was constituted by an epoxyresin of a low viscosity, was applied to each tapered chip mounting hole2 (see FIG. 1). At this time, a very small amount of the sealant oradhesive 5 was applied by transfer using a transfer pin.

Next, each tapered IC chip 4 b on the foregoing pallet was chucked by anozzle having a diameter of 1.5 mm and having a suction hole formedcentrally of a nozzle tip, then was transferred and inserted and fixedinto the corresponding tapered chip mounting hole 2.

In this way an upper surface (the side where the electrodes 3 areformed) of each tapered IC chip 4 b and an upper surface of the resinfilm substrate 1 could be made contiguous to each other without formingany difference in height between the two; besides, the chip could beinserted and fixed into the hole rapidly.

Thus, the tapered IC chip 4 could be easily mounted on the resin filmsubstrate 1 with only the electrodes 3 exposed above the substratesurface (see FIG. 11). Subsequently, a circuit pattern 14 for connectionwith the electrodes 3 of the tapered IC chip 4 was formed. Morespecifically, using a screen printing machine, a conductive paste withsilver grains dispersed about 70% therein was printed to form a circuitpattern 14 having a circuit width of 1 mm and a thickness of about 25μm.

As a result, there could be formed one turn of closed circuit antennawherein both ends of the circuit pattern 14 were extended onto andconducted with the plural electrodes 3 of the tapered IC chip 4.

Lastly, a cover film constituted by a 100 μm thick polyester alloy filmwas heat-laminated at 200° C. onto the upper surface of the resin filmsubstrate 1 with the tapered IC chips 4 buried therein, followed bycutting into a card size of 10 mm×50 mm, to afford thin non-contact typetags each having a thickness of about 200 μm.

EXAMPLE 2

A resist was applied onto a 50 μm thick wafer 7 obtained in the same wayas in Example 1, followed by drying, and the only aluminum electrodeportions (a first conductor layer 9 portion of conductor pattern 6) wereexposed to light through a photomask and removed by development,allowing only the aluminum electrodes to be exposed.

Then, the wafer 7 was treated with plasma to remove the oxide filmformed on the surface of each aluminum electrode, then TiW and Au werelaminated by sputtering in this order to the wafer to thicknesses ofabout 0.5 μm and 0.05 μm, respectively, and lastly the resist was peeledoff. As a result, the laminated metal layer was removed from the otherportion than the aluminum electrodes (first conductor layer 9) of eachtapered IC chip and an under-barrier metal layer 10 having a totalthickness of about 0.55 μm was formed on only each of the aluminumelectrodes.

Next, the whole surface of the wafer 7 was coated with a photosensitiveepoxy resin, followed by again going through the exposure/developmentstep and heat-hardening step, to form a 15 μm thick insulating pattern 8on the whole surface of the wafer except the portions where the aluminumelectrodes were formed (see FIG. 5).

Then, the wafer was subjected to full cutting (only the wafer was cut)into the chip size in the same way as in Example 1 to obtain tapered ICchips 4 a with electrodes 3 formed thereon and having a taper angle θbof 45 degrees.

Subsequently, the tapered IC chips were inserted and fixed into thetapered chip mounting holes 2 in the resin film substrate 1 through thesame step as in Example 1. At this time, the upper surface (the sidewhere the electrodes 3 are formed) of each tapered IC chip 4 a and thatof the resin film substrate 1 could be made contiguous to each other soas not to form a difference in height between the two.

In this way the tapered IC chip 4 a could be mounted easily to the resinfilm substrate 1 with the electrodes 3 exposed above the substratesurface (see FIG. 11).

Subsequently, a circuit pattern 14 for connection with the electrodes 3was formed on the resin film substrate 1. More specifically, using ascreen printing machine, a conductive paste with silver grains dispersedabout 70% therein was printed to form a circuit pattern having athickness of about 30 μm. At the same time, the conductive paste wasalso printed onto the under-barrier metal layer 10.

Thus, here again there could be formed one turn of closed circuitantenna wherein both ends of the circuit pattern 14 were extended ontoand conducted with plural electrodes 3 of each tapered IC chip 4 a.

Next, the same cover film as that used in Example 1 was heat-laminatedto the upper surface of the resin film substrate 1 at 220° C., followedby cutting into a card size of 10 mm×50 mm, to afford thin non-contacttype tags each having a thickness of about 200 μm.

EXAMPLE 3

A wafer 7 with only aluminum electrodes (a first conductor layer 9 ofconductor pattern 6) formed on the surface thereof was affixed to asupport film, followed by full cutting (only the wafer was cut) into achip size of 0.6 mm×0.8 mm from the back side with use of a diamondblade having a bevel-cut tip, to afford tapered IC chips 4 each havingelectrodes 3 and having a taper angle θb of 45 degrees. Each tapered ICchip had sixteen electrodes of a 50 μm square at 100 μm pitches, with noinsulating pattern formed thereon.

Then, the tapered IC chips 4 were separated from the support film andarranged in regular order on a pallet fabricated by a nickelelectroforming method.

On the other hand, tapered chip mounting holes 2 having a taper angle θaof 45° were formed by a UV laser method in a resin film substrate 1constituted by a 100 μm thick polyester film and then an epoxy sealant 5low in viscosity was applied a very small amount to each tapered chipmounting hole 2 with use of a transfer pin. Further, the tapered ICchips 4 were each chucked and transferred by means of a nozzle having atip diameter of 0.5 mm and having a central suction hole 0.2 mm indiameter and were inserted and fixed into the corresponding tapered chipmounting holes 2.

Also in this case an upper surface (the side where the electrodes 3 areformed) of each tapered IC chip 4 and that of the resin film substrate 1could be made contiguous to each other so as not to form a difference inheight between the two and the insertion and fixing of the chip could bedone rapidly.

Next, the whole of the upper surface of the resin film substrate 1 wascoated with a photosensitive epoxy resin and a 10 μm thick insulatingpattern 8 was formed on the entire wafer surface except the aluminumelectrode portions (the first conductor layer 9 portion) through anexposure/development step and a heat-hardening step.

Subsequently, the resin film substrate 1 was treated with an alkalinesolution to remove an oxide film formed on the surface of each aluminumelectrode, followed by activation treatment, thereafter, the substrate 1was immersed in an 85° C. electroless nickel plating bath for 15 minutesto form a nickel plating layer of about 2 μm on only the aluminumelectrodes, followed by further immersion in an electroless gold platingbath at 90° C. for 5 minutes to form a gold plating layer of 0.05 μm,i.e., an under-barrier layer 10, on the nickel plating layer.

Next, a 0.6 μm thick aluminum film was formed throughout the wholesurface of the resin film substrate 1 by sputtering and a resist wasapplied onto the aluminum film, followed by drying, then a wiringcircuit image was formed by exposure and development and thereafteraluminum present in apertures of the resist was removed using analuminum etching solution to form a circuit pattern 14 of aluminum.

EXAMPLE 4

The same procedure as in Example 3 was repeated up to the step offorming the 10 μm thick insulating pattern 8 on the whole wafer surfaceexcept aluminum electrode portions.

Next, the oxide film on the surface of each aluminum electrode wasremoved by treatment with plasma, then Ni and aluminum were formed intofilms of 0.05 μm and 0.6 μm respectively by sputtering, thereafter aresist was applied onto the aluminum film and dried, followed byexposure and development to form a wiring circuit image, then thealuminum present in each aperture of the resist was removed using analuminum etching solution to form a circuit pattern 14 of aluminum.

INDUSTRIAL APPLICABILITY

According to the present invention, as set forth above, when a COFpackage is to be obtained by the IC chip buried type manufacturingmethod, each IC chip can be buried so as not to be dislocated to alarger extent than a predetermined limit, so it is possible to form acircuit pattern accurately (so as not to cause a larger positionaldeviation than a predetermined limit) relative to electrodes of the ICchip and hence possible to obtain a COF package of a constant quality.

Moreover, by pressing a resin film substrate with use of a heatedtapered die to form chip mounting holes or by cutting a wafer havingconductor patterns with use of a grinding rotary cutter so as to formtapered cut faces, thereby providing IC chips formed with electrodes, itis possible to mass-produce COF packages of a constant quality.

1. A method of manufacturing a COF package, comprising the steps ofproviding a resin film substrate having a chip mounting hole, providingan IC chip having electrodes, inserting said IC chip into said chipmounting hole so as to fix it with its electrodes exposed above asurface of said substrate, and forming a circuit pattern on thesubstrate surface for connection with said electrodes, wherein said chinmounting hole and said IC chip are tapered, and said IC chip is fixedinto said chip mounting hole with a sealant or an adhesive, wherein saidsealant or adhesive is replenished in a vacuum atmosphere into a gapformed between said IC chip fixed into said chip mounting hole and saidchip mounting hole.
 2. The method of claim 1, wherein said IC chiphaving electrodes is formed by cutting a wafer having conductor patternsinto a chip size so as to provide tapered cut faces.
 3. The method ofclaim 2, wherein said wafer is cut with use of a grinding rotary cutterso as to provide said tapered cut faces.
 4. The method of claim 3,wherein said chip mounting hole and said IC chip are tapered at the sametaper angle.
 5. The method of claim 4, wherein each conductor pattern isformed on said IC chip and includes an under-barrier metal layer.
 6. Themethod of claim 5, wherein insulating patterns are formed on said ICchip and in contact with said electrodes for insulating said conductorpatterns.
 7. A method of manufacturing a COF package, comprising thesteps of providing a resin film substrate having a chip mounting hole,providing an IC chip having electrodes, inserting said IC chip into saidchip mounting hole so as to fix it with its electrodes exposed above asurface of said substrate, and forming a circuit pattern on thesubstrate surface for connection with said electrodes, wherein said chipmounting hole and said IC chip are tapered and said IC chin is fixedinto said chip mounting hole with a sealant or an adhesive, wherein saidresin film substrate is pressed with a heated tapered die to form saidchip mounting hole.
 8. The method of claim 7, wherein said IC chiphaving electrodes is formed by cutting a wafer having conductor patternsinto a chip size so as to provide tapered cut faces.
 9. The method ofclaim 8, wherein said wafer is cut with use of a grinding rotary cutterso as to provide said tapered cut faces.
 10. The method of claim 9,wherein said chip mounting hole and said IC chip are tapered at the sametaper angle.
 11. The method of claim 10, wherein each conductor patternis formed on said IC chip and includes an under-barrier metal layer. 12.The method of claim 11, wherein insulating patterns are formed on saidIC chip and in contact with said electrodes for insulating saidconductor patterns.